Project ECLipz Surfaces, But Not the Way You Think

November 5, 2007 Timothy Prickett Morgan

Tongues are a-wagging out there again in IT Land about IBM‘s ongoing “Project ECLipz” server convergence initiative. In a PDF document that has an internal name “ECLipz-DCT,” one of the key IBMers responsible for the decimal floating point unit inside the current Power6 and future z6 mainframe engines compares and contrasts the two processors. The Power6, of course, is the chip used in the System i and System p server lines, which support i5/OS, AIX, and Linux.

The good news for mainframe shops is that System z mainframes are going to get a lot more processing oomph and other goodies pulled over from the Power6 processors, as it turns out. Information leaking out about the future z6 processors might be one of the reasons why mainframe sales took a hit in the third quarter, too, and why IBM might have some challenges in the current fourth quarter and into early next year, too.

According to the Project ECLipz document, the z6 chip will be IBM’s first native quad-core chip, packing four cores onto a single die and giving each of them 3 MB of L2 cache memory on the chip. Like prior mainframe processors, the z6 chip will have data compression and cryptographic functions on the chip, and will include the new decimal floating point units that made their debut in the Power6 RISC processors that were announced this summer for the System p and System i lines. (Decimal units do so-called “money math” natively, not with a software overlay on existing integer math units in the chip.) Each core on the quad-core z6 chip has 64 KB instruction and 128 KB data L1 caches, plus a binary/hexadecimal floating point, fixed point, and decimal floating point unit. There are two compression and cryptographic accelerators on the chip, shared by a pair of processor cores.

The future z6 chip implements the IBM mainframe instruction set in 24-bit (System/360), 31-bit (370/XA), and 64-bit (z/Architecture) modes. The chip is not, as many rumors about IBM’s Project ECLipz convergence of its high-end server lines had suggested, simply a Power6 chip with some mainframe window dressing thrown on. The z6 chip has 894 mainframe CISC instructions (with 668 of them implemented in hardware), and supports PR/SM logical partitioning and z/VM instances with assistance from the chip. The pipeline in the z6 cores has been completely redesigned and streamlined to allow IBM to crank up the clock speeds on the unit to 4 GHz and higher, and IBM has also added 50 new instructions to the z6 chip that help compiled mainframe applications run faster.

Like prior and current generations of Power processors from IBM, the z6 chip includes the electronics to link up multiple processors into symmetric multiprocessors on the chip itself, which means IBM will be able to relatively easily link these chips into very large processor complexes. The z6 processor will be married with an SMP hub chip that has 48 GB/sec of bandwidth and has 24 MB of SRAM L3 cache on it. IBM is not yet saying how far it can scale the z6 servers that will use the z6 processor and the SMP hub chip, but it seems likely that a minimum of 16 of these units will allow up to 64 z6 cores to be presented to applications in a single system image for z/OS. That SMP hub chip has a stunning 1.6 billion transistors and a total of 7,984 pins. The SMP hub chips can be paired up in a system, which suggests IBM might be offering pairs for scalability (perhaps pushing cores in the machine up to a maximum of 128) or for reliability (maybe even mirroring processors in the system, which would be an interesting development). IBM’s goal is to have mainframes never go down, and mirroring processors would certainly help accomplish this. Each z6 chip has two 48 GB/sec SMP hub ports, four 13 GB/sec memory ports, and two 17 GB/sec I/O ports.

The z6 chip will have 991 million transistors and 138 MB of SRAM on the die in total. The chip has 1,199 signal pins and a total of 8,765 pins and a die size of 21.7 millimeters by 20 millimeters. Like the Power6 chip, the z6 mainframe chip is implemented in IBM’s 65 nanometer SOI chip processes, and like the Power6 chip, the pipeline has been reworked to do instructions mostly in order at a low latency, allowing clock speeds to rise to boost performance of applications. Other chip makers have decided to preserve their pipelines, keep the clock speeds low, and add multiple cores to get the throughput of a chip up where Moore’s Law can take it. With the Power6 and z6 chips, IBM is trying to stay within the same thermal envelope and allow clock speeds to rise as high as it can push them.

If the Power6 is any guide, then the z6 mainframe processors should offer considerably more performance than their z9 EC predecessors, but not as much as the higher clock speed might lead you to believe. The dual-core z9 EC chip ran at 1.7 GHz and each core delivered around 580 MIPS of performance (the EC Model 701) and an aggregate of 17,800 MIPS in a 54-processor EC Model 754 machine. The clock speed change to 4 GHz and higher and the pipeline shift might yield somewhere around a 50 percent raw performance increase per core, and the radically redesigned SMP hub approach (which is not part of the Power6 machines, at least not yet) could make the machines scale a lot more efficiently and support a lot more main memory as well. So we might be looking at z6 cores with mainframe engines rated around 875 MIPS to 900 MIPS, and if IBM can efficiently push up the core count and get more work out of it, the box could deliver a lot more aggregate MIPS. The current System z9 EC box lets around 43 percent of the aggregate MIPS go up the chimney with its SMP implementation, and just reducing that SMP overhead to 35 percent for a 64-core z6 system would yield a mainframe with around 36,000 MIPS of performance.

A decade ago, when IBM was shipping G4 mainframe engines running at 300 MHz, the 9672 mainframes had a top-end engine speed of around 63 MIPS and a scalability of 10 engines with a total usable MIPS of 447 MIPS. IBM has gradually ramped up mainframe processor clock speeds, hitting 420 MHz in 1998 with the G5s, 550 MHz in 1999 with the G6s, and 770 MHz with the z900 processors in 2000. Those “T-Rex” mainframes sported IBM’s first dual-core mainframe processors, although the company did not say this at the time. (Only half of the processors in a given T-Rex box had both cores working because yields were so low on these chips.) In 2003, with the z990 machines, IBM went to full dual-core processors and boosted clock speeds to 1.2 GHz at the same time, and in 2005, the z9 EC machines launched with dual-core 1.7 GHz chips.

IBM is not yet saying when the z6 chip will be ready for market or when the systems employing this z6 chip will be generally available. Based on the recent stall in mainframe sales, it is reasonable to guess that IBM will try to get the mainframes using the z6 chips to market in early 2008. There has been no talk of seeing these processors or the machines that use them any time this year.

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