IBM, AMD Expect 45-Nanometer Chips in Mid-2008
January 8, 2006 Timothy Prickett Morgan
Chip makers IBM and Advanced Micro Devices have been partners for nearly four years in the development of advanced chip manufacturing processes, and the two announced after we went on vacation that they have made enough progress in three technologies geared for 45 nanometer chip making processes to say that they can get products into the field using two of these technologies by the middle of 2008.
IBM and AMD made the announcement at the International Electron Device Meeting in San Francisco, and researchers from both companies presented papers on three different means of making better chip circuitry: immersion lithography, ultra-low-K interconnect dielectrics, and multiple enhanced transistor strain. AMD and IBM say that they can get two of these technologies–immersion lithography and ultra-low-K interconnect dielectrics–into products within the next 18 months.
The smallness of chip making processes is important because it allows vendors to cram more stuff onto chips and also improve the yield on their chips, since they are smaller. In the past, shrinking a chip also meant its clock speed can be boosted and still stay in the same power envelope, but most chip makers are more interested in adding processor cores rather than cranking up the clocks these days. IBM’s future dual-core Power6 chip is an exception to this rule, and is expected to run near 5 GHz. Most chips run at 3 GHz these days, with a few running at close to 4 GHz.
IBM and AMD are both working to get their next-generation 65 nanometer technologies ramped up in their respective Power and Opteron platforms. AMD just last week started shipping 65 nanometer, low-power variants of its Rev F Opteron processors. And while IBM has been using 65 nanometer processes in its “Cell” PowerPC variant, which is deployed in the Sony PS3 game console as well as IBM’s own BladeCenter blade servers. IBM’s top-end Power5+ server processors, however, only use 90 nanometer processes, and the company has to wait until the Power6 chips in mid-2006 to move to 65 nanometer technologies.
The immersion lithography breakthrough is important because conventional lithographic chip making methods hit a wall at 65 nanometers. In March, IBM and partner JSR Micro showed an immersion lithography technique that scaled down below 30 nanometers. With immersion lithography, the laser light beams that are used to etch circuits into photosensitive material on silicon wafers are focused by a layer of water that surrounds the wafer. Because light slows down when it enters the water, you can crank the light up to a higher frequency, which yields a tighter laser beam, and therefore the ability to etch smaller circuits. If this technique didn’t work, the industry would have probably had to move to X-ray lithography, which would be a very expensive move. Bathing wafers in water before you etch them is a lot cheaper.
The other technology that IBM and AMD are going to get into the field is ultra-low-K dielectric, which is a variant of the low-k dielectric process that ironically creates pores in the insulating portions of circuits (as opposed to the conducting tracks where the electronics are shepherded) and thereby increases their insulating abilities. The problem with shrinking circuits is that the insulating layer gets thinner and thinner, and electromagnetic fields can cause one wire in the circuit to interfere with signals in adjacent wires. Because air is a relatively good insulator–a lot better than the stuff that lithographic techniques can lay down on chips–then making that insulating layer more porous has the non-intuitive effect of making it a better insulator.
All of these three chip technologies are being developed at the Albany Nanotech Center, which is a joint partnership with the state of New York, IBM, and AMD; the processes are being perfected at the 300mm chip making factories of IBM in East Fishkill, New York, and of AMD in Dresden, Germany. AMD and IBM have committed to work together to push through 32 nanometer and 22 nanometer processes, which gets them to about 2011 or so.
The final technology–multiple enhanced transistor straining–will be part of that continuing shrinkage in chip processes. Strained silicon techniques are already used in chip making by IBM, AMD, Intel, and others, and involved stressing the circuits in precise ways to improve the electrical conductivity of circuits.