Power7+ Details To Be Revealed At Hot Chips 24

June 25, 2012 Timothy Prickett Morgan

If all goes well, I will be flying out west in late August to visit Stanford University and the Hot Chips 24 symposium on processors and other types of chips used in the gadgetry around us in the data center and in our offices and homes. It’s a total geek fest, with presentations that are about 75 percent over my head, and the kind of thing I love to do because being a dummy and admitting it is the only way to learn anything.

A whole bunch of server chips are going to be revealed at the Hot Chips event, as you can see from the agenda. Notably for readers of The Four Hundred, IBM will be talking for the first time about the Power7+ processor, which Big Blue has been hinting would come in the second half and that Colin Parris, the new general manager of the Power Systems division, told me back in May at the COMMON midrange conference would be coming out at the end of this year. If history is any guide, that probably means September or October, just in time for a fourth-quarter push.

IBM first divulged some of the feeds and speeds of the Power7 chip back at the Hot Chips event in August 2009, so this is a bit of a ritual.

Not much is known about Power7+, but here is a roadmap that IBM was circulating late last year to partners and customers that has some information on it, which I told you about last August:

The latest IBM Power chip roadmap I can find. (Click graphic to enlarge.)

The Power7+ processor is expected to plug into the existing socket used by Power7-based servers today, but IBM has warned me in the past that there will be other tweaks to the processor that will require customers to swap out system boards as part of an upgrade to Power7+ processors. I happen to think IBM is upgrading the I/O peripheral slots to PCI-Express 3.0, to better compete against Intel‘s eight-core Xeon E5s, which have two PCI-Express 3.0 controllers on chip, etched right onto the ring connecting the cores together. I also think IBM will be upgrading its InfiniBand-derived GX++ bus for linking external peripheral enclosures to the box. But those are just guesses.

What we know is that the chips will run faster as IBM shrinks from its current 45 nanometer to 32 nanometer processes and will also sport more on-chip L3 cache as well as unnamed accelerators. I am guessing that even with this huge increase in transistors by raising the L3 cache size by a factor of 2.5, there will be enough of a shrink on the chip to raise the clock speed on the process by 25 to 30 percent. The combination of the two could significantly increase the single-thread and multithread performance of the Power7+ chip compared to Power7.

If you know something about Power7+, saying something. I will start poking around a bit, too, and I will also get out to Hot Chips to see what else I can find out.

IBM also plans to talk about its “zNext” processor for its System z mainframes, also due before the end of the year, and Oracle will be showing off its forthcoming 16-core Sparc T5, which is expected to hit before the holidays as well. Fujitsu is also trotting out a 16-core Sparc64-X behemoth that it intends to put in its Sparc Enterprise M machines, which may or may not be resold by Oracle.