IBM Pushes Moore’s Law Limits With Carbon Nanotube Transistors
November 5, 2012 Timothy Prickett Morgan
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Silicon-based chip etching technologies are going to reach the lower limits of the atomic scale at some point, and chip equipment and chip designers are all looking out ahead into the future to try to come up with new technologies that will extend or replace current silicon-based chips so out electronics will get faster, more capacious, and less expensive over time, tracking with Moore’s Law. Scientists working at IBM Research in Yorktown Heights, New York, offer one possible tweak to current technology, having come up with a technique that will create chips based on carbon nanotubes, which offer better performance and thermal characteristics than the current exotic materials that etch transistors onto silicon wafers. Carbon is a faster and more efficient transmitter of electrons than the wires that are placed on silicon wafers to make transistors; carbon nanotubes are interlocking chains of carbon atoms that are rolled up like the casing on a coaxial cable. Creating the transistors out of carbon nanotubes is tricky, and then mounting them to silicon wafers using existing machines and processes–which is important to make future chips economically feasible–is a tall order. Chips currently have billions of transistors, woven in intricate patterns. IBM has been monkeying around with carbon nanotubes for a number of years, and earlier this year demonstrated transistors that are only 10 nanometers across, the same scale as conventional transistors are expected to be maybe three nodes from now. (Intel is at 22 nanometers, some others are at 28 nanometers, and IBM’s Power7+ is at 32 nanometers, just for reference.) Making the transistors is easy, getting them to latch onto silicon in precise configurations, not so easy. IBM has come up with a way to use ion-exchange chemistry to place the carbon nanotube transistors precisely on a chip, and in a recent experiment revealed last week, was able to line up 10,000 transistors on a chip. Take a look:
This image above shows a scanning electron microscope (SEM) image of carbon nanotube field-effect transistor (CNTFET) arrays with a pitch of 300 nanometers. IBM says that the source and drain contacts for the devices in the array are connected by metal leads and pads for electrical testing in a semi-automated probe station. None of that matters to you and me, of course. What we want to know if the Power10 processor will use carbon nanotubes. No word from IBM on that, as you might expect. RELATED STORIES IBM Power7+ Chips Give Servers A Double Whammy IBM Off To The Races With New Memory Tech IBM Is One Step Closer to High Speed, Low Power Racetrack Memory Moore’s Law and the Performance Wall Reader Feedback on Moore’s Law and the Performance Wall IBM Goes Vertical with Chip Designs
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