Expect i5/OS V5R5 in 2007, Power6 for System i Maybe in 2007
Published: September 25, 2006
by Timothy Prickett Morgan and Dan Burger
Whenever IBM's top brass in the System i division attends a major trade show event like COMMON, the IBMer in charge of development of the System i platform is always on hand to give a sneak preview of the technologies that Big Blue is putting together for the next release of hardware and software. The COMMON event in Miami Beach was no exception, and Jim Herring, director of System i product management and business operations, was on hand to answer questions.
Because I have been fortunate enough to be called to serve for four weeks in New York State's grand jury--yes, that is heavy sarcasm--I was unable to attend the meeting. But, IT Jungle's Dan Burger was on hand with my questions and a few of his own for Herring, and we learned a bit about the future i5/OS V5R5 operating system and the Power6-based System i servers.
I said "a bit." IBM is still holding its cards pretty close to the vest.
This time last year, Herring and his compatriot from Systems and Technology Group, Vijay Lund, told us a bit about the Power6 processor and even brought one to show off at the fall COMMON. (Lund is vice president of server and storage development for Systems and Technology Group, and he steers the technologies that the different server divisions employ in their products.) Since that time, other details have emerged on the Power6 chip. And the situation warrants a brief recap before getting into the new stuff that Herring told us. Take a deep breath.
Power6: What We Already Know and Suspect
The Power6 chip will have approximately 750 million transistors, and it will us a 65 nanometer process that is being perfected at IBM's chip fabs in Upstate New York. The current Power5+ chips, which scale up to 2.3 GHz, use a 90 nanometer process, and by shrinking to 65 nanometer etchings on the chip, IBM can therefore make smaller circuits and therefore jack up the clock speed of the processor and stay within a given thermal envelope. (IBM could also hold clock cycles steady and let the chip run a lot cooler, and for certain workloads, like blade servers, I would not be surprised to see such a two-pronged approach.) The dual-core module variant of the Power6 chip has what IBM calls its "C4" chip interconnect, which is derived from Big Blue's mainframe technology and which are suspiciously similar to the Socket F interconnect used by Advanced Micro Devices for its "Santa Rosa" Rev F Opteron processors, which were just launched two months ago.
The Power6 chip is a dual-core chip, just like the Power5 and Power5+ chips that preceded it, but it has nearly three times as many transistors. (The Power5+ chip with 1.92 MB of shared L2 cache for the two cores has 276 million transistors.) IBM has said it contains functionality that might have otherwise ended up in custom ASICs on the systems or inside low-level microcode. IBM also said, in February, that the Power6 chips would run in the range of 4 GHz to 5 GHz, and in a surprising move, divulged that the instruction pipeline in the Power6 chip would be about the same length as in the Power5 and Power5+ chips. As with the Power4 and Power5 chips, buses between cache and main memory and I/O interconnections to the outside world, which the Power6 chip uses to get data, will scale up with the clock speed, too. Because IBM has added lots more cache to the chip--exactly how much remains a mystery--the Power6 chip is expected to deliver about twice as much raw performance as the Power5 chip it replaces.
Because thermals and electricity usage have become big issues, the Power6 chip has a distributed clock architecture that will allow different parts of the chip to run somewhat independently. By not having a central clock, you don't have to boost that clock signal so it can reach all ends of the chip (which takes a lot of energy) to keep everything in lockstep. So for a given amount of performance, a Power6 chip should burn a lot less juice than a Power5+ chip. IBM has also hinted that the packaging on the Power6 variants will be similar to that of the Power5+ generation, which means we can expect dual-core modules with either one or two cores activated that plug into a single socket; a quad-core module (QCM) with two whole chips sharing a single socket (new since October 2005 with the first Power5+ chips, and only available in the System p machines, not the System i servers); and multi-chip modules that cram eight cores and four L3 caches on a single piece of ceramic. IBM has not said it if will add L4 cache to the Power6 architecture, but it might. I think it is very likely that IBM doubles the L3 cache to at least 72 MB per chip, and that it introduces an L4 cache on the very largest machines--those in the 590 and 595 class in the current System i and System p lines.
Executives from IBM have said they expect to deliver about twice the raw performance with Power6 compared to Power5, which is in keeping with the performance boost from Power4 to Power5.
What IBM Is Saying Now
According to Herring, IBM is indeed still on plan to deliver the Power6 at the clock speeds it was talking about earlier this spring. "We are looking at somewhere between 4 GHz and 5 GHz on Power6," Herring explained from COMMON. "So it will be significantly faster from a gigahertz perspective. We are trying to match up speed with the products we will create."
But, Herring also cautioned about making too strong of a correlation between processor gigahertz and system performance. "Just because it runs at that gigahertz doesn't mean you get that kind of throughput performance," he said. "There are lots of hardware and software factors associated with performance. We need to get the cache sizes right; we need to get the software tuned for it from the operating system and database perspective. And we want to make sure these things are rock solid before we send them out the door. We monitor all these factors to determine when we can introduce the product."
And that is why we probably won't see the Power6 come out first on the System i platform, according to Herring. "And because it is System i and we have a fairly big software stack, it takes us a little longer than in the System p. They have smaller software stack and a smaller operating system [AIX] than i5/OS. The last time, when IBM introduced Power5, we brought out System i first. This time it might be System p first." He said might be, not will be. So things can still change.
As IT Jungle divulged a year ago, the Power6 generation of servers will have native InfiniBand links, presumably to hook peripherals to systems, like High Speed Loop (HSL) does today as well as to link servers to each other in switched fabrics and to provide another alternative to disk attachment. InfiniBand, which was co-developed by IBM, Intel, and others was originally intended to provide a single type of switched fabric to link servers to each other and to their peripherals.
"We will be introducing InfiniBand on the Power6 systems," Herring reconfirmed. "IBM is investing heavily in InfiniBand, but we haven't seen the take up in the market on InfiniBand that I thought we would, so I think we will leave Power5 and Power5+ with High Speed Link (HSL) technology. We will continue to support HSL and HSL2 with Power6, so customers can migrate over time." Herring said further that IBM will see wider adoption of 10 Gigabit Ethernet in that same time frame, and faster Fibre Channel links, too. "That is one of the trends in our large customer set. We see more people attaching to TotalStorage for flexibility of disk needs in multiplatform situations. They want to plug System i into the same bank of storage that they have everything else plugged into, and we certainly want to support and promote that."
Lagging the industry somewhat, IBM is also expected to get Serial-Attached SCSI (SAS) disk drives into its Power6 systems, too. IBM is using 3.5-inch parallel SCSI disks today. SAS drives come in a new 2.5-inch form factor, which means they are smaller and cooler than their 3.5-inch older brothers. IBM is also expected to beef up disk capacities. "We will ramp up the processor speed and the cache size of our disk adapters so we can get larger disks," Herring said. "Today we have almost transitioned from 35 GB to 70 GB disks. We have a lot of customers buying 70 GB drives. We will start to see a transition to 140 GB and, at some point, probably next year, we will see 300 GB disks in standard parallel SCSI format. These disks will be available for both Power5 and Power6."
So, exactly when will we see Power6-based System i machines? "Whether Power6 is available for System i in 2007 has to do with being able to deliver a high-quality product," Herring explained. "Going back to what I said earlier, our customers have a higher standard because they trust it for applications that can't go down--order-taking systems, manufacturing planning systems, or point of sale systems. We take extra care."
On the software front, Herring said that the future i5/OS V5R5, which would indeed be its moniker (at least the release name part) will add intrusion prevention features to the intrusion detection features that were added in i5/OS V5R4. The TCP/IP stack, for instance, can already see if someone is doing port scans, which is a common way to try to hack into a system.
V5R5 will also have improvements in high availability clustering. With V5R4, IBM introduced a feature called Cluster Administrative Domain, which helps automate the way configuration files for users and peripherals get moved over from a primary to a backup machine. Herring said that about half of the functionality to do smoother recoveries was in V5R4, and that the remaining half would probably be finished with V5R5.
V5R5 will also take iSeries Navigator, which is a Windows-based client/server front end for i5/OS and OS/400 server administration and take it more fully to the Web. "We are going to take the iNav componentry and make it Web enabled," said Herring. "Some of this is available with iSeries Access for the Web, but we will make it much simpler to manage the system through a Web interface. That's a big ticket item we are working on now."
Herring did not say when i5/OS V5R5 would be available. The rumor mill had been suggesting that it might come out in March 2007, and other sources have speculated that it could come out some time in the first half of 2007. But, given that it can take 18 to 25 months between releases, it could turn out that i5/OS V5R5 comes out in late 2007 to early 2008. IBM just isn't saying right now.
IBM Hints at Triple Redundancy in Power6
Power6 Gets Second Silicon, IBM to Crank the Clock
IBM Raises the Curtain a Little on Future Power Chips, i5/OS V5R4
Transcription: Remarks by Vijay Lund and Jim Herring, at COMMON briefing
IBM's Power6 Gets First Silicon as Power5+ Looms