Power6 Ups the Ante for Virtualization, Power Management
November 13, 2006 Timothy Prickett Morgan
Last month, IBM told the world about some of the features that it had built into its future Power6 RISC processors, which are expected to appear in IBM’s System p machines around mid-2007 and maybe in its System i machines around that time, or maybe in late 2007 and perhaps early 2008. Big Blue is being a little vague about exactly when Power6 will come out for reasons it has not specified. But the company is being clear that when it does come out, Power6 will be jammed full of improvements.
As previously reported in this newsletter, the Power6 chip has some interesting features. Like the Power4 and Power5 chips before it, the Power6 chip will be a dual-core chip. IBM is not moving to a quad-core design, but will probably–but not immediately–put two chips in a single processor socket, yielding what is in effect a quad core chip. This is exactly what IBM already does with the Power5+ quad core modules, and what rival Intel will do tomorrow when it launches the “Clovertown” Xeon 5300s. These chips put two of its dual-core “Woodcrest” Xeon 5100 chips in a single package, clocked down a bit to make them run a lot cooler yet still delivering about 50 percent more performance in the same thermal envelope.
The Power6 chip will have a new kind of execution unit that is specifically earmarked for processing the decimal math that is behind so many financial transactions, which is a first for a commercial processor (or, at least as far as I know). Each Power6 core will have its own AltiVec VMX vector co-processor, which does certain kinds of matrix math very fast. The chip has a lot of mainframe-class error detection and recovery electronics, which were detailed in the story that ran a month ago. The Power6 chip will run at between 4 GHz and 5 GHz, and is expected come out closer to the top end of that range.
Two areas where IBM has dedicated a significant amount of resources with the Power6 platform have to do with virtualization and power management. The performance of processors is not the only issue IT managers care about these days. The ability to virtualize machines so workloads can be allocated resources as they need them and to use the least amount of electricity and generate the least amount of heat are becoming equally important. Data centers are busting at the seams, and the expense of building out data centers is causing companies to cram more stuff into the same space. That, of course, drives up power densities in the data center, which creates all kinds of problems.
The virtualization in the Power line of servers resides in microcode underneath the operating system, and in terms of electronics, is involved mostly in the load/store units of the Power processor, according to Brad McCredie, the chief architect of the Power6 processor who works in IBM’s Systems and Technology Group. McCredie says that the Power6 has been implemented to support up to 1,024 virtual machines per chip, which means 512 per Power6 core. The Power4 and Power5 processors had a large number of virtual machines per system–exactly how many, IBM has not said–but the company only implemented a maximum of 254 virtual machines per system. And that number was only available on the largest System i and System p boxes. The Power4 and Power5 machines were enabled to support up to 10 Linux partitions per processor core, or 20 per chip, but they could have–in theory–done more. (IBM throttled the partitions mainly to ensure that each partition would have enough resources to do useful work.)
Clearly, moving from 20 partitions per chip to 1,024 partitions is a big leap. However, McCredie says that the Systems and Technology Group may not implement the logical partitioning at its peak. “We’re probably going to stop at a couple of hundred partitions per chip,” says McCredie. “What the software does has not been disclosed.”
IBM may, of course, have a number of customers who want to be able to support thousands of logical partitions on a Power-based server. Think of all the service providers, who deliver virtual server partitions to customers. Imagine if they wanted to host on a big Power box instead of a collection of rack-mounted X86 servers. If one customer suddenly needed more capacity, it could be dynamically allocated and their Web site would not suffer performance degradation. Or, imagine that you were an ERP software supplier that wanted to offer your code under a Software as a Service (SaaS) pricing model. The same fluidity of virtualized resources and the very fine granularity would be just as useful. Imagine many thousands if not several tens of thousands of partitions, running a very tiny operating system and activating with ERP code only when users started hammering away.
In theory, a top-end Power6 box could support 32,768 logical partitions, and if the Power6 box delivers about twice the performance of the Power5+ machines, that means it could have an aggregate of about 8 million transactions per minute (TPM) of online transaction processing power. That would only leave about 244 TPM of performance per partition. It is not clear if this is enough oomph to support modern code. This is roughly equivalent to a 25 MHz or 33 MHz 486 processor. You probably need around 5,000 TPM or so to get any useful work done for a dozen or two users, which means IBM will officially support at most around 1,600 logical partitions on a Power6 box; but, for customers who have lots of occasional users with a predictable usage pattern, then IBM could offer a special bid machine with maybe 3,000 or 4,000 logical partitions.
McCredie says that the Power6 chip will have a slightly different memory virtualization architecture from the Power5 and Power5+ chips, allowing memory to be reconfigured and moved as partitions move. This feature is called memory packing. The memory subsystems in the machines will also allow system administrators to reconfigure memory allocations around failing memory cards, so these faulty components can be isolated and replaced without taking applications offline. The memory in the Power6 servers will also support virtual page key protection, which means data residing in memory has keys that prevent unauthorized access–like the kind that hackers try to do with their malware.
The other big change coming with the Power6 processors, aside from the core circuits and fine-grained virtualization, is much more sophisticated power management features. The new power management features are known collectively as the PowerExecutive extensions.
Back in May, IBM announced power-throttling capabilities in its Xeon-based servers that support “Dempsey” and “Woodcrest” processors from Intel. PowerExecutive consists of a set of electronics on the server motherboards and systems software that interfaces with it that monitors actual power usage in a machine as workloads are running–and ties the two sets of data together so companies can tie electric use and heat thrown off to workloads. The PowerExecutive tools also allow system administrators to set energy consumption thresholds in the servers.
“PowerExecutive is not so much about the Power6 chip, but about giving customers control,” says McCredie. “Customers always want performance, but they also want flexibility. They want to know how much power the systems are burning as they run their own workloads. We want to make power consumption policy-driven, just as we have done with system provisioning and virtualization.”
PowerExecutive will be able to do a number of things on the Power6 machines. It will be able to watch system utilization and if utilization drops, it will be able to deactivate components to conserve power. If multiple Power6 boxes have workloads that are dropping their utilization, the system administrators will be able to set policies that will enable workloads to be consolidated onto one box rather than onto two boxes. PowerExecutive will also be able to kick down fan speeds if workloads are not stressing the servers (they already ramp up when servers do more work), and it will also tell administrators that if the temperatures in the system are below certain levels, they can boost the performance of workloads and get jobs to finish earlier. Once a boosted application is finished doing its work, circuits can be turned way down.
To make all of this happen, the Power6 processors have been equipped with many thermal sensors, and the system boards have sensors to measure power consumption in different areas of the machine. The controller that implements the PowerExecutive features is called Empath, and it hooks into the Power6 processor, the server’s system processor, the power modules, and the power measurement points around the system.
IBM Uncloaks Power6 Chip Details
IBM to Offer Automatic Power Throttling on Servers
IBM Hints at Triple Redundancy in Power6
Power6 Gets Second Silicon, IBM to Crank the Clock
IBM Raises the Curtain a Little on Future Power Chips, i5/OS V5R4
Some More Thoughts on the Future Power6 Chips from IBM