Brace Yourself For A Bevy Of Server Chip Announcements

February 8, 2010 Timothy Prickett Morgan

It’s either feast or famine in the processor racket, and this week will see two server chips being announced and others being previewed for launch later in the quarter. All of the new chips coming out have their enthusiasts–some will even buy systems that use them!–and each chip will find its niche or volumes, as the case may be, despite the homogenization pressure in the systems sector.

As The Four Hundred reports elsewhere in this issue, IBM is rolling out the first of its Power7-based systems today in New York as part of a much wider Smarter Planet marketing initiative. (Smarter Planet is the new Dynamic Infrastructure that is the new On Demand that is the new eBusiness. I probably forgot a bunch of other over-arching, or perhaps over-reaching, marketing initiatives.) On the left coast, in San Francisco, at the International Solid State Circuits Conference, IBM will be drilling down into the guts of the Power7 chips, talking about the 45 nanometer processes that are used to make the eight-core Power7s. (I walked you through the known features of the Power7 chips here last August and then here again in September as I got some more data and chewed on it for a bit. (See the Related Stories section below for all of my thinking on the impending Power7 systems and the i 7.1 operating system.)

Interestingly, IBM will also be showing off a whole different Power7-derived chip at ISSCC, one that crams 16 cores onto a single piece of silicon and that runs as high as 2.3 GHz. Each core has four processor threads, like the Power7, and dissipates 65 watts of heat when running at 2 GHz and a very low 0.85 volts. By adding cores and stepping down the clock speed and volts, IBM’s abstract for the experimental Power7 chip says that it can cut power consumption in half.

At ISSCC, Intel is lifting the veil a bit on its “Gulftown” Westmere-EP Xeon processors for two-socket X64 servers. The news coming out of ISSCC is that the Gulftown chips will cram six cores onto a single die and 12 MB of on-chip L3 cache memory, which is 50 percent more cores and L3 cache than last year’s “Gainestown” Nehalem-EP processors, which are sold as the Xeon 5500s. The quad-core, eight-threaded Nehalem-EPs have been largely responsible for keeping the server business from falling completely on its keister during the economic meltdown. (The six-core “Istanbul” Opteron 2400s and 8400s did their part, too, when they were rolled out last summer.)

The six-core Westmere-EP chips, which are implemented in a 32 nanometer high-metal gate process and have 1.17 billion transistors, use essentially the same cores as the Nehalem-EPs, except that this core has been tweaked to have native instructions for performing data encryption and decryption algorithms used in the Advanced Encryption Standard, and the on-chip DDR3 main memory controllers have been modified so they can support low-voltage DDR3 memory DIMMs as well as the regular ones. The low-voltage memory runs at 1.35 volts and dissipates 20 percent less heat than normal 1.5 volt parts with the same capacity and frequency. The other change with the Westmere-EPs is that not only do the cores have power gating as the Nehalem-EPs did, but now the L3 cache and memory controller regions of the chips do as well. This means that cores, cache, and memory controllers can be shut down when not in use by applications, saving lots of electricity and cutting down on the heat the chip generates. As IBM is doing with the Power7s, Intel plans to package up Westmere-EP semi-duds and sell them. Chips that only have four working cores will be available to server buyers alongside the six-core parts.

The Westmere-EP chips will plug into the same sockets as the Nehalem-EPs and run at about the same clock speeds, which means the performance improvements come only through the additional cores. Intel is expected to announce the Westmere-EP chips in the middle of March, and kick out its eight-core “Beckton” Nehalem-EX chips for high-end Xeon boxes by the end of March. In a separate event on February 8, Intel will also roll out its long-awaited “Tukwila” quad-core Itanium processors, which are mostly important for Integrity systems sold by Hewlett-Packard. The Tukwila chips have been delayed again and again for years and are expected to deliver about twice the oomph as the current 1.66 GHz dual-core “Montvale” Itanium 9100s.

While AMD is not showing off its eight-core and 12-core “Magny-Cours” Opteron 6100 chips at ISSCC, it will be previewing the core design in its “Fusion” family of desktop and mobile processors, which will cram a graphics processor and a central processor onto the same chip. While that is all well and good, the Opteron 6100s and their servers are what data centers really care about; these are expected to come out at the end of March and to be rolled into two-socket and four-socket systems over the spring and summer, followed in short order by the four-core and six-core “Lisbon” Opteron 4100s for servers with one or two sockets. AMD is making its own chipsets for these chips, too. You can read all that I know about the chips and chipsets here.

Oracle has completed its acquisition of the former Sun Microsystems, and will next week attend ISSCC as well, with its chip engineers showing off the “Rainbow Falls” Sparc T3 series chips. The Sparc T3 is a 16-core Sparc chip with eight threads per core; it will be used in machines with one, two, or four processor sockets. The chip is only expected to run at 1.67 GHz–about the same speed as Intel’s Tukwila, but less than half the speed of the cores on IBM’s Power7s and about half the speed of the Westmere-EP, Nehalem-EX, and Magny-Cours X64 chips. The Sun, now Oracle, design calls for a lot more threads running at lower clock speeds, which Sun, now Oracle, contends offers better performance per watt on the kinds of workloads that Sun and Oracle have traditionally focused on: database and middleware. These workloads, and the Java applications that Oracle sells, know how to balance across lots of threads.

If you don’t think the combined Oracle-Sun is a threat to IBM, you ain’t been reading this newsletter closely enough.

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