IBM And Samsung Go Vertical To Push Transistor Density On Chips
January 10, 2022 Timothy Prickett Morgan
Big Blue might have sold off its IBM Microelectronics chip fabrication operation to GlobalFoundries many years ago, but that does not mean that the company does not still do a reasonably large amount of fundamental research into chip maker techniques and tricks. Transistor, chip, and packaging research and development is a big portion of the patent portfolio at IBM and continues to be so because Big Blue still has some of the smartest chipheads on the planet working for it because IBM wants to ensure there is a roadmap for future Power and System z processors and because it can make money licensing the technologies it creates to the fabs of the world.
Just after we went on holiday break in the middle of December, IBM and Samsung announced that they have been working together on a new chip making technique called Vertical Transport Field Effect Transistor, or VTFET, which is a different technology from the 2 nanometer nanosheet transistor technology that IBM was bragging about developing last May.
Both the nanosheet stacked transistor technology announced in May and the VTFET technology announced in December are follow-on techniques to the FinFET 3D transistor techniques that have been used for the past several generations of processor and networking chips (starting with the 16 nanometer and 14 nanometer nodes, generally speaking) that have allowed for more efficient transistors and therefore have allowed their geometries and thus their costs to keep shrinking relative to older 2D planar transistor manufacturing techniques.
The details of the advance that IBM and Samsung have made while working together at the Albany Nanotech Complex in upstate New York are quite hairy, and in fact were done in conjunction with Globalfoundries prior to 2018 according to the acknowledgment in the paper presented at the IEDM 2021 conference last month. You can get the paper here if you want to take a look at it, and here is a blog post that explains it a little bit better.
But here is the idea: Instead of creating the transistor from layers of material stacked up on a silicon wafer, the transistor design is rotated 90 degrees and stood up off the wafer and then its features are created vertically. (Imagine turning a layer cake on its side, with vertical stripes of cake and icing instead of horizontal ones.) Here is what it really looks like, with the VTFET on the left and the FinFET on the right:
By making this simple change, the physical constraints on transistor gate length, spacer thickness, and contact size between elements of the transistor can be relaxed and also they can be optimized for high performance (where they are thicker and burn more electricity) or lower power (where they are thinner but have more leakage).
IBM’s and Samsung’s initial test chips have allowed twice the performance on the transistor or an 85 percent reduction in power used in transistors made using FinFET processes. (It is not clear at what node level these comparisons have been made.) When IBM was showing off its 2 nanometer chip making research last year in May, the nanosheet stacked transistor technique IBM was discussing was compared to a 7 nanometer FinFET device and offered a 45 percent performance improvement or a 75 percent reduction in power consumption. It is not clear if the nanosheet stacked transistor and VTFET techniques can be added to each other, but if not, then there are two ways to get some more transistor density and therefore to drive Moore’s Law a little bit longer.
And that is a good thing for the Power11, Power12, and Power13 processors way out there in the future.