The Power11 Transistor Count Discrepancies Explained – Sort Of

August 25, 2025 Timothy Prickett Morgan

One of the perplexing things about the Power11 announcement is that we know that the differences in the logic and cache designs of the Power10 and the Power11 server chips are not huge, and yet the transistor count jumped by almost a power of two from the Power10 to the Power11.

This didn’t make sense to us, and we said as much during the Power11 launch back in early July. (Our observations about transistor count discrepancies were made after our initial story ran and once we got our hands on the drafts for Power11 Redbooks. In those Redbooks, tables said the Power11 chip has 30 billion transistors, a clock speed that ranges from 3.8 GHz to 4.4 GHz, and a 654 mm² die size. The Power10 chip, the Redbooks said, had 18 million transistors, clock speeds of between 3.75 GHz and 4.15 GHz, and a 602 mm² die size. We saw places where the Power11 was said to have only 18 million transistors.

We are not sure what the extra 52 mm² area of the Power11 die is doing, which we frankly forgot to ask about, but thanks to an explanation from Bill Starke, chief architect of the Power10 and Power11 processors and has been involved in the designs of many generations of Power chips from IBM.

As it turns out, IBM has historically not been counting all of the transistors in a device, as the rest of the industry does, in its Power and System z chips.

“We have had our own very proprietary tools flow,” Starke tells The Four Hundred. “Your transistor counting comes out of your tools flow. We have historically counted the transistors that were actively and logically representing digital zeros and ones in the system – the actual functional logic of the system. But there are a lot of other transistors used in other ways when you’re building a semiconductor like this. As we started using some of the industry standard flows, such as with our Spyre AI chips, and they tabulated a transistor count for Spyre that was then publicized and advertised, and that led to some internal discrepancies, like engineering analysis. What we discovered was that those tools which are counting the way the industry counts, and they count more transistors than we historically have.”

Much of the discrepancy between the old way and the new way, at least for Power10 and Power11, came from what are called decap cells, which is short for decoupling capacitor cells, which are comprised of CMOS transistors and which are used to storage electric power close to the circuits and stabilize the power delivery and reduce the noise on the signal of the power inputs for the chip.

According to a cursory search of server chip designs that I have done, in server chips in general, the number of decap cells used to represent a fraction of a percent of the total transistors, but in more advanced nodes today (5 nanometer processes) it can be as high as 5 percent. Cache memory, depending on the hierarchy of L1, L2, and L3 caches on the chip, and the “uncore” regions of the chip used to network elements of a processor together, can represent somewhere between 65 percent and 80 percent of the total transistor count. The remaining 15 percent to 35 percent of the transistors are represented by the processors cores, controllers, and accelerators in the design.

For IBM to have somewhere around 12 million decap cells, representing around 40 percent of the total transistor budget rather than around 5 percent, is a new piece of data. And this might explain in part how well IBM can do power gating and power deliver so well in its Power chip designs, and perhaps more significantly, drive clock speeds up between 4 GHz and 5 GHz on a given N process when the rest of the industry is struggling to get to 3 GHz on a server CPU on an N+1 process.

It may turn out that decap cells are a strategic advantage for IBM’s chip designers.

These decap cells would be distributed evenly across the Power10 and Power11 designs and would not show up in the chip block diagrams as such. Take a look at Power10, which is essentially the same as Power11:

If make some rough estimates base don how the lines are drawn here, and we fully realize that the white lines overlaid on the chip image that delineate chip blocks are fat relative to the size of the circuitry, you would find that somewhere around 85 percent of the area is for L1, L2, and L3 caches. About 10 percent is for core logic, with the I/O controllers, memory controllers, and on-chip interconnect accounting for maybe 5 percent. The only thing that makes sense is that the decap cells are spread around the whole chip.

So, to estimate it further and make our best guesses: Power11 has 30 billion transistors, with around 15 billion used L1, L2, and L3 caches, 12 billion of them used for decap cells, around 2 billion used for the CPU cores (minus the L1 and L2 caches of course), and about 1 billion used for I/O and memory controllers and on-chip interconnect. To make this make sense, either the Power11 chip was literally larger than Power10 by 52 mm² using a revised 7 nanometer process to improve the yield in some fashion, has more decap cells, or has some other feature we don’t know about hidden. If the area is larger and there are more transistors on Power11 than Power10, it could be that Power11 has even more decap cells. If you do the math backwards, then Power10 would have 11 billion decap cells instead of the 12 billion used in Power11 to make the area and transistor counts work out.

This is all conjecture, of course. But, what we do know is that the transistor counts between Power10 and Power11 didn’t change much, the area didn’t change much, and they are very similar chips with a few microarchitecture tweaks and a much better power distribution system. We will tell you all about that next week.

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