It’s A Good Thing For IBM That Samsung Makes Chips And Also Runs A Foundry
October 10, 2022 Timothy Prickett Morgan
Over the decades, Big Blue has invested an enormous sum of money – easily equal to hundreds of billions of dollars in inflation adjusted 2022 dollars – to figure out clever ways to etch transistors on silicon wafers and to package them up into chips that it and other companies used in commercial and consumer products. It was a great business right up to the minute it wasn’t, mostly because IBM’s chip volumes were getting smaller and smaller at the same time the cost of creating successively smaller transistors was getting larger and larger.
And so, back in 2014, IBM tapped out instead of taping out, and paid GlobalFoundries $1.5 billion to take its Microelectronics chip making business over and to also continue making the 22 nanometer Power8 chips it was already shipping, to perfect the 14 nanometer processes it was already developing for the Power9 chips, and to take over development of 10 nanometer extreme ultraviolet (EUV) chip etching for the Power chips.
As we all know, it didn’t quite work out that way. As IBM revealed in a lawsuit it filed against GlobalFoundries in June 2021, GlobalFoundries could not perfect its 10 nanometer EUV process (just like Intel can’t seem to do either) and tried to move the delayed Power10 chip to a 7 nanometer EUV process, and then in August 2018 it spiked the whole thing and said it was going to focus on 12 nanometer and larger geometries that were already working (and perfected, we might add, with the help of Big Blue). This not only hurt IBM, but it also hurt AMD, and luckily for AMD, it was already a partner of Taiwan Semiconductor Manufacturing Co, the largest foundry in the world, thanks to its graphics card business. IBM was a semiconductor process development partner with Samsung (just like AMD and Nvidia are) and Samsung wanted to take its foundries up another notch from making chips for smartphones and tablets to making server chips – we think possibly as a pretext to entering the Arm server chip arena, or at least to get some of the action among Ampere Computing, Amazon Web Services, Alibaba, and HiSilicon, which all make Arm server chips.
But none of that matters directly to IBM i shops. What they care about is that IBM has a stable foundry partner in Samsung, and that there is a process and packaging roadmap running out into the next 10 years when Power11, Power12, and Power13 processors will come into being if history is any guide.
Whether or not Power processor history is any guide to the future is subject to debate, and a subject for another story on another day. . . .
The important thing is that Samsung is a CPU and memory maker and it already has a mature 7 nanometer process (7LPP) and a mature 5 nanometer process (SF5E) that can be tweaked for server chips, which require slightly more robust transistors than client devices. Samsung has line of sight to get to 4 nanometer, 2 nanometer, and 1.4 nanometer process technologies to drive its own business, and Big Blue gets to come along for the ride while offering its substantial expertise in transistors and packaging to help it along – much as IBM did with GlobalFoundries before and after the sale of the Microelectronics division. For a price, of course. Big Blue has never done something for free. IBM has not said what processes it will use for future chips – we have been strongly encouraging Big Blue to do a socket-compatible Power10+ kicker about a year and a half from now, perhaps using a 5 nanometer process, but we highly doubt the company will listen to our logic.
We know Power11 is on the design books and we would not be surprised if IBM waits until Power11, which will probably be a dual-chip implementation of what is essentially four 16-core Power10 chips in a single socket. Power10 is already a dual-chip module, you will remember, with anywhere from 1 to 12 of its 16 total cores activated, and by doing a shrink to 5 nanometers, IBM could probably double up the cores and therefore nearly double the throughput of Power Systems iron. Clock speeds would probably have to drop a bit, of course, to stay in the right thermal design points. Power11 will probably have some microarchitecture improvements, and there might even be enough changes for there to be an increase in instructions per clock (IPC) for integer, vector, and matrix operations. The IPC improvements could balance out against the clock speed decreases to boost the per-socket throughput by 2X or more. We shall have to see.
Samsung has just announced that its 3 nanometer SF3 family of processes, which incorporate gate-all-around (GAA) nanosheet 3D transistor designs has been used in several tapeouts and is delivering 30 percent more transistor performance in 30 percent less area with 50 percent less power consumption than the 5 nanometer SF5E process.
At its tech forum event last week, Samsung was also talking about a rev on its 4 nanometer SF4E process, which is being used for mobile processors, with a new SF4X process aimed at what it calls “HPC applications” that delivers 25 percent more performance than the base SF4E process from which it is derived. This SF4 process is an intermediary node, like TSMC’s custom 4N process created initially for Nvidia’s current “Hopper” GH100 GPUs and future “Grace” Arm server CPUs, which sits between TSMC’s 5 nanometer and 3 nanometer processes.
This Samsung SF4X process could also be used for a future Power10+ or Power11 chip, but you have to remember that any advanced process – particularly those using EUV technologies – is more expensive. In recent years, IBM has been willing to hang back a little bit on process to intersect a mature and less costly process, and we don’t see that changing. But Samsung says that the SF4 processes have lower defect density than the SF5 processes and a faster ramp up, and that might make it a better choice for a potential Power10+ or Power11 chip.
At the Samsung Foundry Forum last week, Samsung also said that it plans to expand its production capacity for the advanced process nodes by 3X by 2027 and that it was targeting mass production of 2 nanometer manufacturing by 2025 and 1.4 nanometer processes by 2027. (It looks like Samsung might be skipping the 1.8 nanometer node that Intel is working on and calls 18A.) These advanced nodes will use GAA nanosheet designs, as will similar processes from TSMC and Intel, the only other advanced foundries in the world today. Samsung is also being more aggressive with its 2D and 3D packaging technologies, and we would not be surprised to see IBM had vertical caches to its Power chips as AMD is doing with the current “Milan-X” Epyc 7003s and future “Genoa-X” Epyc 9000s.
Samsung also said that non-mobile chips – what it calls automotive and HPC chips, the latter portion including IBM Power CPUs – would exceed 50 percent of its “foundry portfolio” by 2027. That sounds like customer count and design count, not wafer or chip count. But it is a lot more than Samsung had five years ago or has now.
The point here is that Samsung is committed to customers like IBM, and is thrilled to have captured the Power and System z chip business that GlobalFoundries abandoned. The other point is that IBM has options if it wants to be more aggressive with its Power CPU line. We do not think IBM is in a mood to be aggressive, and is playing the datacenter very conservatively after the OpenPower Consortium did not have the desired effect of expanding the Power ecosystem and finding partners to help shoulder the cost of maintaining and expanding that ecosystem and its architecture.